Wafer Level Chip Scale Pacakaging - Solder Joint Reliability

This paper will discuss the solder joint reliability aspects of a new wafer level Chip Scale Package (CSP) form factor. The CSP requires no leadframe or interposer tooling. It is the same size as the die, and was originally developed for low-pin count analog devices for pitches from 0.8 mm down to 0.5 mm. The package has been demonstrated with eutectic solder bumps on 8-lead devices. The form factor can be extended to higher pin counts of up to 144. Underfilling is not required. Various Design of Experiments (DOEs) were performed to determine the best combination of geometry and process parameters that will yield the best thermal cycling performance. The paper will present highlights of the study, in addition to a description of the solder joint performance.